ASIC Intern
Description
As an ASIC Intern at Etched, you will have the opportunity to work in one of the following areas: RTL, Physical Design, or Design Verification. RTL interns will help design and implement the digital logic that powers our ASICs. Physical Design interns will be responsible for working to implement and verify physical designs, and will help Etched as we work to improve iteration speed on physical design. Design Verification interns will ensure the custom IPs powering Sohu — including systolic arrays, DMA engines, and NoCs — are robust, high-performance, and silicon-ready.
Details
- Location
- San Jose, CA
- Term
- Summer 2026
- Posted
- 1/19/2026