Intern Processing-in-Memory 🎓

Description

We are seeking a highly skilled and motivated Next-Generation Memory Solution Engineer to drive innovation in energy-efficient memory technologies. The ideal candidate will work on the research, development, and optimization of advanced memory architectures that integrate processing capabilities for enhanced computing performance.

Responsibilities:

  • Research and develop next-generation memory architectures and solutions to improve computational efficiency.

  • Design and optimize memory-centric computing systems for AI, HPC, and data-intensive applications.

  • Collaborate with hardware and software teams to integrate next-generation memory solutions into existing and future computing platforms.

  • Develop memory access patterns, data flow optimizations, and power-efficient architectures for memory solutions.

  • Work on memory controller design, data movement optimization, and system-level performance analysis.

  • Conduct benchmarking and validation of new memory technologies in real-world applications.

  • Stay up-to-date with industry trends in next-generation memory, AI accelerators, and computing architectures.

  • Engage with research communities, publish findings, and contribute to technical conferences and patents.

Minimum Qualifications:

  • Master's degree in Electrical Engineering, Computer Engineering, or a related field.

  • Strong understanding of memory architectures (e.g., DRAM, HBM) and their role in modern computing.

  • Knowledge of hardware/software co-design principles and memory hierarchy optimizations.

  • Proficiency in C/C++, Python, or related programming languages.

  • Familiarity with simulation tools for memory performance analysis and system modeling.

Preferred Qualifications:

  • Ph.D. in a relevant field with research experience in Processing-in-Memory (PIM) or near-memory computing.

  • Experience with AI/ML accelerators, FPGA prototyping, or custom hardware design.

  • Understanding of parallel computing, GPU architectures, and HPC.

Details

Location
San Jose, CA
Term
Summer 2026
Posted
1/22/2026

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